ISL29011
I 2 C Electrical Specifications
tolerance, 16-bit ADC operation. (Continued)
For SCL and SDA unless otherwise noted, V SUP(VDDD,VDDA) = 3V, T A = +25°C, R EXT = 499k ? 1%
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 9)
TYP
(Note 9)
UNIT
C i
Capacitance for each SDA and SCL pin
10
pF
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R
t F
t SU:STO
t BUF
C b
R pull-up
t VD;DAT
t VD:ACK
V nL
V nH
Hold Time (Repeated) START Condition
LOW Period of the SCL clock
HIGH period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Rise Time of both SDA and SCL Signals
Fall Time of both SDA and SCL Signals
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Capacitive Load for Each Bus Line
SDA and SCL System Bus Pull-Up Resistor
Data Valid Time
Data Valid Acknowledge Time
Noise Margin at the LOW Level
Noise Margin at the HIGH Level
After this period, the first clock pulse
is generated.
Measured at the 30% of VDD crossing
Maximum is determined by t R and t F
600
1300
600
600
30
100
20 + 0.1xC b
20 + 0.1xC b
600
1300
1
0.1VDD
0.2VDD
400
0.9
0.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
k ?
μs
μs
V
V
NOTE:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6
FN6467.5
October 10, 2012
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